The ADC ADC data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital con- verter 8-channel multiplexer and. ADC ADC – 8-bit Microprocessor Compatible A/D Converters With 8- Channel Multiplexer, Details, datasheet, quote on part number: ADC The ADC/ADC Data Acquisition Devices (DAD) implement on a single chip most the elements of the stan- dard data acquisition system. They contain.

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Datasheeh signal can be tie to the ALE signal when the clock frequency is below kHz. The ADC stores the data in a tri-state output latch until the next conversion is started, but the data is only output when enabled. On the rising edge of the pulse the internal registers are cleared and on the falling edge of the pulse the conversion is initiated.

At clock speeds greater than that the user must make certain that enough time has passed since the ALE signal was pulsed so that the correct address is loaded into the multiplexer before a conversion begins.

National Semiconductor

Top rail of Reference voltage. It goes low when a conversion is started and high at the end of a conversion. The OE signal should conform to the same qdc0809 as all the other control signals. You will also need to download multiplex. Address Lines Because the chip has an 8 channel multiplexer there are three address select lines: The maximum clock frequency is affected by the source impedance of the analog inputs.


Daasheet that it can take up to 2. The voltage level that, when received as an input, will output “” to the FPGA.

Up to 72 if the start signal is received in the middle of an 8 clock cycle period. That is because ADCs require clocking and can contain control logic including comparators and registers.

ADC Technical Data

It is the LSB of the select lines. It is the MSB of the select lines. It is the Second bit of the select lines.

datashdet This is an address select line for the multiplexer. The start signal should conform to the same range as all other control signals.

Source code The source code consists of a few of files. This means that an entire conversion takes at least 64 clock cycles.

Bottom rail of Reference voltage. For a quick reference refer to table 2. In this implementation the OE signal is pulsed high one clock cycle after the EOC signal goes high and remains high until the data is safely stored into the desired register in the FPGA. Table 2 provides a summary of all of the input and output to the chip. It is a control signal from the FPGA, which tells the converter when to start a conversion.

Clock The clock signal is required to cycle through the comparator stages to do the conversion. C is the most significant bit and A is the least.


The source resistance must be below 10kohms for operation below kHz and below 5kohms for operation around 1. It can be tied to the Start line if the clock is operated under kHz. The ALE should be pulsed for at least ns in order for the addresses adtasheet get loaded properly.

Signal from the ADC. Be sure to consult the manufactures data-sheets for other chips. This means it must remain stable for up to 72 clock cycles. All of the signals are explained below. This means that in order to get it to work, there is a total of seven control signals that must be sent from the FPGA. Begin by downloading the files into your desired destination directory and then compile them in this order. All control signals should have a high voltage from Vcc – 1.

It is recomended that the source resistance not exceed 5kohms for operation at 1. A, B, and C. Start The purpose of the start signal is two fold. Unfortunately you cannot just hook up analog inputs to an ADC and expect to get digital outputs from the chip without adding control signals.

The clock should conform to the same range as all other control signals. There are a couple of limitations that follow: